Example embodiments of inventive concepts relate to a non-volatile memory device, and more particularly, to a method of operating a memory controller for increasing the speed of a read operation of a non-volatile memory device and reducing a read failure rate and a memory system including the memory controller.
Examples of memory devices used to store computer programs and data are dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, and phase-change random access memory (PRAM). Especially, flash memory is non-volatile memory that is capable of enabling electrical reading.
Single-level cell (SLC) memory is memory that stores data of one bit in a single memory cell. SLC memory may also referred to as single-bit cell (SBC) memory. Data of one bit may be written to and read from SLC memory by a voltage belonging to one of two distributions distinguished by a threshold voltage programmed to a memory cell.
Data stored in a memory cell may be classified depending on the difference between memory cell currents/voltages during a read operation. Meanwhile, multi-level cell (MLC) memory that stores data of two or more bits in a single memory cell has been proposed in response to a need for higher integration of memory. MLC memory may also be referred to as a multi-bit cell (MBC) memory.
However, as the number of bits stored in a single memory cell increases, reliability may deteriorate and the read-failure rate may increase. To program “m” bits in a single memory cell, 2 m distributions may be required to be formed. However, since the voltage window of a memory may be limited, the difference in a threshold voltage between adjacent bits may decrease as “m” increases, which may increase the read failure rate.
The threshold voltage distribution of an MLC may change over time due to coupling effect, charge loss, or the like. Moreover, the threshold voltage distribution of the MLC may change with temperature. In order to reduce (and/or minimize) a bit error rate (BER), it is desirable to relatively accurately estimate a read level in a non-volatile memory device.
Flash memory may perform an erase operation in units of memory blocks and may perform a program operation and a read operation in units of pages.
In a conventional method of estimating a read level, when a page that has been read has uncorrectable errors, a read voltage level may be adjusted and the data of the page may be re-read using the adjusted read voltage level. For instance, when least significant bit (LSB) page data that has been read has uncorrectable errors in flash memory including MLCs, an LSB read voltage level may be adjusted and the LSB page data may be re-read using the adjusted read voltage level in the conventional method.
However, this conventional method may not be used to estimate a most significant bit (MSB) page read voltage level when MSB page data read from flash memory including MLCs has uncorrectable errors.